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| .'''p''' [[ https://patents.google.com/patent/US2875141A | patent ]] for germanium thickness measurement during etching. rTansmission intensity drops (interference?), then rises until desired thickness is reached. | .'''p93''' [[ https://patents.google.com/patent/US2875141A | patent ]] for germanium thickness measurement during etching. rTansmission intensity drops (interference?), then rises until desired thickness is reached. But Philco was going downhill. .'''p97''' 1955 APS paper "base widening punch through" read by William Schockley. Noyces moved to California Feb 23, bought house morning before job interview. .'''p99-106'''[[ https://en.wikipedia.org/wiki/Gordon_Moore | Gordon Moore ]] Redwood City / 2y San Jose State, Betty Whitaker 1950 UCB / !CalTech / JHU telemetry / applied to GE, hired by Schockley .'''p108''' Moore "negative entrepreneur", escaping prior unhappy job .'''p109''' [[ attachment:moores-law-electronics.pdf | April 19, 1965 Electronics Article ]] .'''p111''' Rice and chessboard story, "halfway down the board, he has already committed to all the rice in China". Perhaps loose with "halfway", if 50K grains per kilogram, 200kg per million grains, then 2^33 grains (squares 1 to 32) is 170 metric tonnes. Current production is 200 million tonnes, 20 more squares; historically, production might be 1/16th of that, so 16 more squares and 2 more rows. I'd call that 3/4 of the way down the board. The exponential analogy is apt, but the description is sloppy. The author (a reporter) should test his statements (reporters rarely do). .'''p112''' ''"memory chips capable of storing more than one trillion bytes"'' ... ''nope.'' In 2014, a dense memory process might be 20nm linewidth, and a 4 level/2 bit memory cell might be 40 by 40 nanometers. One trillion bytes is 4 trillion 2 bit memory cells, 2 million cells on a side (not counting periphery and driver cells). 2 million times 40 nanometers would be a chip more than '''8 centimeters''' on a side ... probably a lot more. Again, the reporter/author should learn to use a calculator. No citations; [[ https://en.wiktionary.org/wiki/POOMA | POOMA? ]] . [[ https://en.wikipedia.org/wiki/Moore's_law | From wikipedia:]] ''In 2019, Samsung produced a 1 TB flash chip with eight stacked 96-layer V-NAND dies, along with quad-level cell (QLC) technology (4-bit per transistor), equivalent to 2 trillion transistors, the highest transistor count of any IC chip'' that's a terabyte, but 8 stacked chips. [[ https://www.electronicsweekly.com/news/business/samsung-makes-1tb-flash-module-2019-01/ | This article ]] mentions 16 layers, not 96. As of 2020/03, Samsung has just introduced a 512GB product. .'''p133''' 1969 Intel first product 3101 64 bit Schottky TTL SRAM, 2x faster than Fairchild's . "didn't leak power" ?huh? 525 mW [[ attachment:INTLS0327-1.pdf | datasheet ]], 16 pins, 4 bits, 4 address, 35 to 50ns . [[ http://www.righto.com/2017/07/inside-intels-first-product-3101-ram.html | recent teardown ]], also 74S289 .'''p136''' 1101, 256 bit static nmos silicon gate SRAM [[ attachment:1101.pdf | datasheet ]] 8 address din/dout 16 pin 1.5us |
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The Intel Trinity
How Robert Noyce, Gordon Moore, and Andy Grove Built the World's Most Important Company
Michael S. Malone 2014 BvtnLib 338.7621 MAL
Some interesting factoids. Some may be incorrect. I may add a few notes later, but I would prefer to do so from a revised edition with less redundancy, more explanation, and citing more sources (many of this book's references are Malone's other books, not primary sources, NOT useful).
I enjoyed Leslie Berlin's excellent The Man Behind the Microchip, and Grove's autobiography and management books.
I want to know more about Gordon Moore ("Trinity" was aggravatingly sparse) so ordered a used copy of Moore's Law: the Life of Gordon Moore by Thackray, 2015 through Alibris.
p4 David Packard managing HP during WW2 (Hewlett served in Signal Corps). Established targets, trusted (female) employees to learn how to meet them.
p5 Lockheed Sunnyvale largest employer in late 1940s
p12 Shockley Semiconductor: Photolithography Bob Noyce and Jay Last, Diffusion Gordon More and Jean Hoerni, Crystals Sheldon Roberts, 2n696 double-diffused-base transistor Victor Grinich and Murray Siegel, investors Eugene Kleiner.
p14 visionary Noyce presentation to Sherman Fairchild
p18 1959 trade show TI integrated circuit, led to Fairchild ICs with planar transistors
p21 error: Hired manager Ed Baldwin left in 1959 (with Fairchild IP, and the mesa process, but NOT Hoerni's planar process) to start Rheem, which failed in 1961.
p22 Charles Spork, Don Valentine (later VC, Something Ventured), Jerry Sanders, Mike Markkula, Jack Gifford (Intersil, AMD, Maxim), Bob Widlar.
p24 Marshal Cox
p25 Andy Grove UCB PhD Chemistry, hired 1964
- Andy Grove's 1967 text "Physics and Technology of Semiconductor Devices" earned me my first summer job at Tektronix in 1969(?).
p26 Lester Hogan at Motorola, later to Intel in 1969.
p27 (cite?) Spring 1965 conference, Noyce announced all major Fairchild ICs for one dollar
p31 error: Widlar sheep, not goat
p32 1966 Fairchild, 12000 employees, $130M sales, Spork and Widlar left for National Semiconductor
- Andy Grove's 1967 text "Physics and Technology of Semiconductor Devices"
p36 Fairchild belittled Noyce, Noyce hired Hogan to replace himself (huge salary and options)
p44 1968 Noyce, Moore, Arthur Rock start Intel, p46 Grove (as employee) follows Moore
p48 Grove recruits Les Vadász Malone obsesses about Grove's dislike of Noyce
p54 Silicon gate MOS
p55 500K × $5 shares convertable debentures, interest-paying IOUs convertable to stock at IPO
p57 $100K investment in 1968 would be $3 billion in 2014
p61 Electronics News January 11 1971 Don Hoefler dateline "Silicon Valley"
Robert Noyce
p62 Noyce born 1927/12/12 Denmark (SE) Iowa father Ralph Congregational minister, Oberlin wife/mother Harriet
- Oldest brother Donald Sterling Noyce May 1923, 1948 Chemistry prof at UCB, died November 2004
p65 Ralph to Atlantic Iowa, then Decorah, then 1938 Webster City (demomination's associate superintendent), then Grinnell
p70 12yo Bob and older brother Gaylord (1925-2009) build a glider
- youngest brother Ralph Harold Noyce
p74 Odd jobs for Grinnell College physics professor Grant Gale (1903-1998) (who also taught Herbie Hancock)
p84 graduates Grinnell 1949, MIT 19xx Professors John Slater and Wayne Nottingham
p88 musicals lead performer, meets Betty Bottomley9 1930-1996) at Tufts
p90 A Photoelectric Investigation of Surface States on Insulators
p92 Philco R&D under Bill Bradley
p93 patent for germanium thickness measurement during etching. rTansmission intensity drops (interference?), then rises until desired thickness is reached. But Philco was going downhill.
p97 1955 APS paper "base widening punch through" read by William Schockley. Noyces moved to California Feb 23, bought house morning before job interview.
p99-106Gordon Moore Redwood City / 2y San Jose State, Betty Whitaker 1950 UCB / CalTech / JHU telemetry / applied to GE, hired by Schockley
p108 Moore "negative entrepreneur", escaping prior unhappy job
p111 Rice and chessboard story, "halfway down the board, he has already committed to all the rice in China". Perhaps loose with "halfway", if 50K grains per kilogram, 200kg per million grains, then 2^33 grains (squares 1 to 32) is 170 metric tonnes. Current production is 200 million tonnes, 20 more squares; historically, production might be 1/16th of that, so 16 more squares and 2 more rows. I'd call that 3/4 of the way down the board. The exponential analogy is apt, but the description is sloppy. The author (a reporter) should test his statements (reporters rarely do).
p112 "memory chips capable of storing more than one trillion bytes" ... nope. In 2014, a dense memory process might be 20nm linewidth, and a 4 level/2 bit memory cell might be 40 by 40 nanometers. One trillion bytes is 4 trillion 2 bit memory cells, 2 million cells on a side (not counting periphery and driver cells). 2 million times 40 nanometers would be a chip more than 8 centimeters on a side ... probably a lot more. Again, the reporter/author should learn to use a calculator. No citations; POOMA?
From wikipedia: In 2019, Samsung produced a 1 TB flash chip with eight stacked 96-layer V-NAND dies, along with quad-level cell (QLC) technology (4-bit per transistor), equivalent to 2 trillion transistors, the highest transistor count of any IC chip that's a terabyte, but 8 stacked chips. This article mentions 16 layers, not 96. As of 2020/03, Samsung has just introduced a 512GB product.
p133 1969 Intel first product 3101 64 bit Schottky TTL SRAM, 2x faster than Fairchild's
"didn't leak power" ?huh? 525 mW datasheet, 16 pins, 4 bits, 4 address, 35 to 50ns
recent teardown, also 74S289
p136 1101, 256 bit static nmos silicon gate SRAM datasheet 8 address din/dout 16 pin 1.5us
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